Small Area High Speed Configurable FFT Processor

This paper presents a design of a configurable FFT processor. The processor can support up to 4096-point FFT, using radix-2(3) algorithm which is optimized. The FFT processor can be configured as two structures which are pipeline structure and iterative structure. Pipeline structure is adopted at 512-point FFT operation and below. If FFT points are more than 512, iterative structure will be activated. The method of accessing the memory is also optimized. Because using multiple butterfly unit to process the data in parallel, the throughput can be improved. Finally, the function simulation and verification is made based on FPGA. The result shows that the processor performs well while utilizing less hardware resource.