Probabilistic fault detection and the selection of measurements for analog integrated circuits

被引:22
作者
Wang, ZH [1 ]
Gielen, G [1 ]
Sansen, W [1 ]
机构
[1] Katholieke Univ Leuven, Dept Elect Engn, ESAT, MICAS Div, B-3001 Heverlee, Belgium
关键词
analog test; test generation;
D O I
10.1109/43.720321
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
New methods for analog fault detection and for the selection of measurements for analog testing (wafer probe or final testing) are presented, Using Bayes' rule, the information contained in the measurement data and the information of the a priori probabilities of a circuit's being fault free or faulty are converted into a posteriori probabilities and used for fault detection in analog integrated circuits, with a decision Criterion that considers the statistical tolerances and mismatches of the circuit parameters. An adaptive formulation of the a priori probabilities is given that updates their values according to the results of the testing and fault detection, In addition, a systematic method is,proposed for the optimal selection of the measurement components so as to minimize the probability of an erroneous test decision. Examples of DC wafer-probe testing as well as production testing using the power-supply current spectrum are given that demonstrate the effectiveness of the algorithms.
引用
收藏
页码:862 / 872
页数:11
相关论文
共 8 条
[1]  
BANERJEE P, 1982, P IEEE INT C CIRCUIT, P546
[2]  
Edwards AWF, 1972, LIKELIHOOD ACCOUNT S
[3]   FAULT-DETECTION AND CLASSIFICATION IN LINEAR INTEGRATED-CIRCUITS - AN APPLICATION OF DISCRIMINATION ANALYSIS AND HYPOTHESIS-TESTING [J].
EPSTEIN, BR ;
CZIGLER, M ;
MILLER, SR .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (01) :102-113
[4]   TOLERANCE ASSIGNMENT FOR IC SELECTION TESTS [J].
MALY, W ;
PIZLO, Z .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (02) :156-162
[5]   VLSI YIELD PREDICTION AND ESTIMATION - A UNIFIED FRAMEWORK [J].
MALY, W ;
STROJWAS, AJ ;
DIRECTOR, SW .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1986, 5 (01) :114-130
[6]   DETECTION OF CATASTROPHIC FAULTS IN ANALOG INTEGRATED-CIRCUITS [J].
MILOR, L ;
VISVANATHAN, V .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (02) :114-130
[7]   MINIMIZING PRODUCTION TEST TIME TO DETECT FAULTS IN ANALOG CIRCUITS [J].
MILOR, L ;
SANGIOVANNIVINCENTELLI, AL .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (06) :796-813
[8]  
WANG Z, 1994, P INT C COMP AID DES, P495