POSITIVE AND NEGATIVE BIAS TEMPERATURE INSTABILITY ON SUB-NANOMETER EOT HIGH-K MOSFETS

被引：30

作者：

Cho, Moonju ^{[1
]}

Aoulaiche, Marc ^{[1
]}

Degraeve, Robin ^{[1
]}

Kaczer, Ben ^{[1
]}

Franco, Jacopo ^{[3
]}

Kauerauf, Thomas ^{[1
]}

Roussel, Philippe ^{[1
]}

Ragnarsson, Lars A. ^{[1
]}

Tseng, Joshua ^{[2
]}

Hoffmann, Thomas Y. ^{[1
]}

Groeseneken, Guido ^{[3
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] IMEC, TSMC, Louvain, Belgium

[3] Katholieke Univ Leuven, ESAT Dept, Louvain, Belgium

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

NBTI; PBTI; thin EOT; high-k dielectrics;

D O I：

10.1109/IRPS.2010.5488667

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, additionally to the oxide bulk trap filling which is the dominant mechanism in over 1nm EOT devices. For NBTI, interface degradation remains as the main mechanism in sub-nano EOT devices, and additional high contribution of the high-k bulk defects can increase the degradation below 6A EOT.

引用

页码：1095 / 1098

页数：4

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