Cu Bump Flip Chip Package Reliability on 28nm Technology

As Cu bump is widely adopted in microelectronic IC product packages for broader scope of applications throughout network communication and handheld device, it impacts on the interconnection joint integrity of package substrate to IC pad need to be well understood and managed which becomes even more critical as extreme Low-k (ELK) inter-metal dielectric material (IMD), with lower mechanical strength, is used in IC fabrication technology of current mainstream 28nm technology. Besides Cu bump joint reliability, the Cu bump joint stress induced ELK delamination defect of IC chip is the major concern due to high rigidity of Cu bump. Two flip-chip package types, mainly flip-chip BGA with 25x28 mm(2) die and flip-chip CSP with 7x8 mm(2) die for covering broader product application range, were evaluated for Cu bump impact on ELK delamination defect. By package assembly T0 CSAM check on various bump schemes and package types, the results showed that the remaining solder gap between the Cu pillar of Cu bump and the pad surface of substrate pad is the dominant factors to IC ELK delamination defect, followed by the IC/substrate pad offset issue at flip-chip reflow temperature issue. The study suggests that minimum of 10um solder gap post Cu bump joint to package substrate prevents the linkage of Cu/Ni/solder IMC (Inter-Metallic Compound) in the solder gap which creates a high stress path to IC ELK through the Cu pillar during flip-chip reflow. For large die Cu bump flip-chip packaging, minimum of 15um solder gap shall be requested to provide more stress buffer to sustain the high thermo-mechanical stress induced by flip-chip mount reflow process. The IC/substrate pad offset optimization is found being critical for preventing ELK delamination in large die package by minimizing Cu pillar induced high bending stress and solder wetting on Cu pillar side wall induced bump joint solder gap decrease.