A Low-Memory-Access Flexible Architecture for FFT

Because memory access is a major cause of power dissipated by the long-length Fast Fourier Transformation (FFT) architecture, this paper explores the design space expanded by FFT size and radix number in detail and presents a novel low-memory-access flexible architecture for computing any long-length 2(n)-point FFT. The proposed hardware solution possesses the following attractive features to reflect its novelty as compared to the existing designs. First, the authors identified that memory consumes major energy dissipation of a FFT processor and proposed to reduce memory access through decreasing the number of FFT butterfly stages. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture. Such low-memory-access flexible architecture can reduce almost 70% memory access or 30% power consumption for FFT computation.