Two-dimensional materials enabled next-generation low-energy compute and connectivity

被引:12
作者
Pal, Arnab [1 ]
Agashiwala, Kunjesh [1 ]
Jiang, Junkai [1 ]
Zhang, Dujiao [1 ]
Chavan, Tanmay [1 ]
Kumar, Ankit [1 ]
Yeh, Chao-Hui [1 ]
Cao, Wei [1 ]
Banerjee, Kaustav [1 ]
机构
[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA
关键词
FIELD-EFFECT TRANSISTOR; MEMRISTIVE CROSSBAR ARRAYS; NEGATIVE CAPACITANCE; EPITAXIAL-GROWTH; POWER; HETEROSTRUCTURES; INTERCONNECTS; INTEGRATION; PERFORMANCE; NETWORK;
D O I
10.1557/s43577-022-00270-0
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Since the invention of the metal-oxide-semiconductor field-effect transistor (MOSFET) in late 1959, the impact of electronics on human society has been increasingly pervasive, heavily regulating modern health, transport, finance, entertainment, and social media sectors through "Big Data." However, daily generation of petabytes of data from these sectors, along with their associated communication overhead, is placing an immense strain on the conventional computing and communication technologies, which were not developed exclusively for big data. Tackling these problems calls for a holistic overhaul of the current semiconductor technology, from materials to architecture, and two-dimensional (2D)-layered materials with their exotic electrical and structural properties are well positioned to accomplish just that. This perspective article aims to provide an overview of the key technological innovations in the nanoelectronics domain that have been achieved with 2D-materials thus far, and to bring forth the promise of this new materials family in developing brain-inspired ultra low-energy on-chip computing and communication techniques to usher a new era in electronics.
引用
收藏
页码:1211 / 1228
页数:18
相关论文
共 143 条
  • [1] Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias
    Agashiwala, Kunjesh
    Jiang, Junkai
    Yeh, Chao-Hui
    Parto, Kamyar
    Zhang, Dujiao
    Banerjee, Kaustav
    [J]. 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [2] Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias
    Agashiwala, Kunjesh
    Jiang, Junkai
    Parto, Kamyar
    Zhang, Dujiao
    Yeh, Chao-Hui
    Banerjee, Kaustav
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (04) : 2083 - 2091
  • [3] Ajayan Pulickel, 2016, Physics Today, V69, P38, DOI 10.1063/PT.3.3297
  • [4] Electrical contacts to two-dimensional semiconductors
    Allain, Adrien
    Kang, Jiahao
    Banerjee, Kaustav
    Kis, Andras
    [J]. NATURE MATERIALS, 2015, 14 (12) : 1195 - 1205
  • [5] PROPOSAL FOR SURFACE TUNNEL TRANSISTORS
    BABA, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 1992, 31 (4B): : L455 - L457
  • [6] 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
    Banerjee, K
    Souri, SJ
    Kapur, P
    Saraswat, KC
    [J]. PROCEEDINGS OF THE IEEE, 2001, 89 (05) : 602 - 633
  • [7] A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    Banerjee, K
    Mehrotra, A
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (11) : 2001 - 2007
  • [8] Global (interconnect) warming
    Banerjee, K
    Mehrotra, A
    [J]. IEEE CIRCUITS & DEVICES, 2001, 17 (05): : 16 - 32
  • [9] Nonvolatile Memories Based on Graphene and Related 2D Materials
    Bertolazzi, Simone
    Bondavalli, Paolo
    Roche, Stephan
    San, Tamer
    Choi, Sung-Yool
    Colombo, Luigi
    Bonaccorso, Francesco
    Samori, Paolo
    [J]. ADVANCED MATERIALS, 2019, 31 (10)
  • [10] Nonvolatile Memory Cells Based on MoS2/Graphene Heterostructures
    Bertolazzi, Simone
    Krasnozhon, Daria
    Kis, Andras
    [J]. ACS NANO, 2013, 7 (04) : 3246 - 3252