Admittance extraction and analysis for through silicon vias near edge and at corner of silicon substrate

被引:0
作者
Liu, Sheng [1 ]
Tang, Wanchun [2 ,3 ]
Huang, Cheng [1 ]
Zhu, Jianping [1 ]
Zhuang, Wei [2 ,3 ]
机构
[1] Nanjing Univ Sci & Technol, Dept Commun Engn, Nanjing, Jiangsu, Peoples R China
[2] Nanjing Normal Univ, Jiangsu Key Lab Optoelect Technol, Nanjing, Jiangsu, Peoples R China
[3] Jiangsu Ctr Collaborat Innovat Geog Informat Reso, Nanjing, Jiangsu, Peoples R China
关键词
electric admittance; silicon; method of moments; three-dimensional integrated circuits; elemental semiconductors; integrated circuit design; admittance extraction; admittance analysis; silicon substrate; through silicon vias; method of moment; image method; wave propagation mode; silicon-outer region interfaces; TSV; Si; COMPUTATIONAL ELECTROMAGNETICS CEM; SELECTIVE VALIDATION FSV; CAPACITANCE MATRIX; THROUGH-SILICON; INTERCONNECTS; INTERPOSER; MODELS; TSVS;
D O I
10.1049/iet-map.2015.0373
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Due to the charge at the interfaces between the silicon substrate and its outer region, the admittance of the through silicon vias (TSVs) near the edge and at the corner of the silicon is different from that of the centre case, which is hardly calculated by conventional empirical formulas. Utilising the method of moment combined with the image method in this study, those admittances can be easily extracted. The difference on the admittance between edge/corner and centre cases is discussed with the frequency and the wave propagation mode. The influence of the distance to the silicon-outer region interfaces and pitches of the TSVs on the admittance are also evaluated and compared in edge and corner cases. The scope of the conventional empirical formulas is also given for the admittance calculation of TSVs in edge/corner case, in order to offer help for the TSVs design.
引用
收藏
页码:1345 / 1351
页数:7
相关论文
共 17 条
  • [1] COMPUTATION OF CAPACITANCE MATRIX FOR SYSTEMS OF DIELECTRIC-COATED CYLINDRICAL CONDUCTORS
    CLEMENTS, JC
    PAUL, CR
    ADAMS, AT
    [J]. IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 1975, 17 (04) : 238 - 248
  • [2] Parameter extraction for on-chip interconnects by double-image Green's function method combined with hierarchical algorithm
    Dai, WL
    Li, ZF
    Mao, JF
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2005, 53 (07) : 2416 - 2423
  • [3] Feature selective validation (FSV) for validation of computational electromagnetics (CEM). Part I - The FSV method
    Duffy, Alistair P.
    Martin, Anthony J. M.
    Orlandi, Antonio
    Antonini, Giulio
    Benson, Trevor M.
    Woolfson, Malcolm S.
    [J]. IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2006, 48 (03) : 449 - 459
  • [4] Modeling of Crosstalk in Through Silicon Vias
    Engin, A. Ege
    Narasimhan, Srinidhi Raghavan
    [J]. IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2013, 55 (01) : 149 - 158
  • [5] Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects
    Han, Ki Jin
    Swaminathan, Madhavan
    Jeong, Jongwoo
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2015, 5 (01): : 108 - 118
  • [6] TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs
    Kim, Dae Hyun
    Mukhopadhyay, Saibal
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (09) : 1384 - 1395
  • [7] Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects
    Kim, Kiyeong
    Hwang, Chulsoon
    Koo, Kyoungchoul
    Cho, Jonghyun
    Kim, Heegon
    Kim, Joungho
    Lee, Junho
    Lee, Hyung-Dong
    Park, Kun-Woo
    Pak, Jun So
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2012, 2 (12): : 2057 - 2070
  • [8] Capacitance and Conductance of Through Silicon Vias With Consideration of Multilayer Media and Different Shapes
    Liu, Sheng
    Tang, Wanchun
    Zhuang, Wei
    Wang, Gui
    Chow, Yung Leonard
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2015, 5 (02): : 256 - 264
  • [9] Analytical, Numerical-, and Measurement-Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)
    Ndip, Ivan
    Zoschke, Kai
    Loebbicke, Kai
    Wolf, M. Juergen
    Guttowski, Stephan
    Reichl, Herbert
    Lang, Klaus-Dieter
    Henke, Heino
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (03): : 504 - 515
  • [10] High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes
    Ndip, Ivan
    Curran, Brian
    Loebbicke, Kai
    Guttowski, Stephan
    Reichl, Herbert
    Lang, Klaus-Dieter
    Henke, Heino
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (10): : 1627 - 1641