Scheduling instructions of sequential algorithms on parallel DSP architectures

被引：0

作者：

Matase, Stelian ^{[1
]}

Costinescu, Bogdan ^{[1
]}

Stoica, Madalin ^{[1
]}

机构：

[1] Motorola DSP Ctr, Bucharest, Romania

来源：

OPTIM 2004: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON OPTIMIZATION OF ELECTRICAL AND ELECTRONIC EQUIPMENT, VOL 4: APPLIED ELECTRONICS, ELECTRICAL ENGINEERING EDUCATION | 2004年

关键词：

integer division algorithms; parallel DSP architecture; StarCore (TM); optimizations; time complexity analysis;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The use of a parallel architecture is suitable for efficient implementation of the algorithms having a certain degree of parallelism. Typically, it is a misconception that the sequential algorithms cannot take advantage of the parallel architecture features. In this paper we present a relevant example to illustrate how a sequential algorithm can be efficiently implemented on a parallel DSP architecture: the integer division algorithm. An enhanced version of the integer division algorithm is presented together with an optimization oriented to the Motorola's StarCore (TM) processor. A short comparative time complexity analysis is encompassed for the proposed algorithm as well as some experimental results.

引用

页码：39 / 42

页数：4