Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile Memories

被引:7
作者
Abu Zubair, Kazi [1 ]
Gurumurthi, Sudhanva [2 ]
Sridharan, Vilas [2 ]
Awad, Amro [1 ]
机构
[1] North Carolina State Univ, Dept ECE, Raleigh, NC 27606 USA
[2] Adv Micro Devices Inc, RAS Architecture, Santa Clara, CA USA
来源
PROCEEDINGS OF 54TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2021 | 2021年
关键词
Non-Volatile Memory; Memory Security; Memory Reliability; PERFORMANCE;
D O I
10.1145/3466752.3480066
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Although emerging Non-Volatile Memories (NVMs) are expected to be adopted in future memory and storage systems, their nonvolatility brings complications in designing processors wherein security is an essential requirement. One of these complications is maintaining the correctness of the security metadata for encryption and integrity verification. Due to the accommodation of security metadata in the NVMs, they are susceptible to reliability threats posed by the underlying memory technology. This is undesirable because the secure operation of the system highly depends on the correctness of the security metadata stored in the memory. We observe that the error sensitivity of security metadata is higher than general data and requires special attention. A single uncorrectable error in a top Merkle tree node can leave a large portion of memory data unverifiable. To solve this, we propose Soteria, a scheme that provides higher error-tolerance of security metadata by lazily duplicating them. Soteria decouples existing memory reliability from the security metadata reliability and achieves security, performance, and high reliability within the same system with only minor memory controller changes. Our proposed scheme improves the reliability of the improved security NVM system significantly while causing only about 1% system slowdown on average.
引用
收藏
页码:1214 / 1226
页数:13
相关论文
共 47 条
[1]   Anubis*: Ultra-Low Overhead and Recovery Time for Secure Non-Volatile Memories [J].
Abu Zubair, Kazi ;
Awad, Amro .
PROCEEDINGS OF THE 2019 46TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '19), 2019, :157-168
[2]  
[Anonymous], 2014, MEMORY FORUM CONJUNC
[3]  
[Anonymous], 2006, ACM SIGARCH Computer Architecture News, DOI [DOI 10.1145/1186736.1186737, 10.1145/1186736.1186737]
[4]   Multilevel-Cell Phase-Change Memory: A Viable Technology [J].
Athmanathan, Aravinthan ;
Stanisavljevic, Milos ;
Papandreou, Nikolaos ;
Pozidis, Haralampos ;
Eleftheriou, Evangelos .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2016, 6 (01) :87-100
[5]  
Awad A, 2018, Arxiv, DOI arXiv:1810.09438
[6]   Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers [J].
Awad, Amro ;
Manadhata, Pratyusa ;
Haber, Stuart ;
Solihin, Yan ;
Horne, William .
ACM SIGPLAN NOTICES, 2016, 51 (04) :263-276
[7]  
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
[8]   HiNFS: A Persistent Memory File System with Both Buffering and Direct-Access [J].
Chen, Youmin ;
Shu, Jiwu ;
Ou, Jiaxin ;
Lu, Youyou .
ACM TRANSACTIONS ON STORAGE, 2018, 14 (01)
[9]  
Chhabra S, 2011, ISCA 2011: PROCEEDINGS OF THE 38TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P177, DOI 10.1145/2024723.2000086
[10]   Reducing Refresh Power in Mobile Devices with Morphable ECC [J].
Chou, Chiachen ;
Nair, Prashant ;
Qureshi, Moinuddin K. .
2015 45TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, 2015, :355-366