Analyses and design of bias circuits tolerating output voltages above BVCEO

被引:31
作者
Veenstra, H
Hurkx, GAM
van Goor, D
Brekelmans, H
Long, JR
机构
[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands
[2] Delft Univ Technol, NL-2628 CD Delft, Netherlands
关键词
avalanche breakdown; bias current source; current mirror;
D O I
10.1109/JSSC.2005.852829
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Due to the inevitable tradeoff between speed and breakdown voltage, the spectacular speed improvement of modern SiGe processes in recent history has partially been achieved at the cost of a reduction in breakdown voltages. Because supply voltages have hardly been reduced however, circuits operating at a supply voltage above the collector-emitter breakdown voltage (BVCEO) are common practice today and collector-base avalanche currents are therefore of major concern. Transistors that need to handle a collector-emitter voltage above (BVCEO) are typically found as output transistors in output driver. stages and in bias current circuits. Such circuits can be designed to tolerate collector-emitter voltages above (BVCEO) by driving the base terminal with a relatively low impedance. This paper analyzes various conventional as well as two new bias current circuits supporting operation at collector voltages above (BVCEO). In the new circuits, feedforward and feedback avalanche current compensation techniques are introduced that obtain a substantial increase in output breakdown voltage of the bias circuits and improve the accuracy of the current mirror at output voltages above (BVCEO). With the feedback technique, a measured increase in output breakdown voltage by more than 2 V is demonstrated while the accuracy of the current mirror ratio at output voltages of 2 to 3 times (BVCEO) is improved by an order of magnitude.
引用
收藏
页码:2008 / 2018
页数:11
相关论文
共 12 条
[1]  
DEGRAAFF HC, 1994, 00694 NLUR PHIL RES
[2]   QUBiC4X:: An fT/fmax=130/140GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications [J].
Deixler, P ;
Rodriguez, A ;
De Boer, W ;
Sun, H ;
Colclaser, R ;
Bower, D ;
Bell, N ;
Yao, A ;
Brock, R ;
Bouttement, Y ;
Hurkx, GAM ;
Tiemeijer, LF ;
Paasschens, JCJ ;
Huizing, HGA ;
Hartskeerl, DMH ;
Agarwal, P ;
Magnee, PHC ;
Aksen, E ;
Slotboom, JW .
PROCEEDING OF THE 2004 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2004, :233-236
[3]   QUBiC4G:: A fT/fmag=70/100GHz 0.25μm low power SiGe-BiCMOS production technology with high quality passives for 12.5Gb/s optical networking and emerging wireless applications up to 20GHz [J].
Deixler, P ;
Colclaser, R ;
Bower, D ;
Bell, N ;
De Boer, W ;
Szmyd, D ;
Bardy, S ;
Wilbanks, W ;
Barre, P ;
van Houdt, M ;
Paasschens, JCJ ;
Veenstra, H ;
vander Heijden, E ;
Donkers, JJTM ;
Slotboom, JW .
PROCEEDINGS OF THE 2002 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2002, :201-204
[4]   40-Gb/s circuits built from a 120-GHz fT SiGe technology [J].
Freeman, G ;
Meghelli, M ;
Kwark, Y ;
Zier, S ;
Rylyakov, A ;
Sorna, JS ;
Tanji, T ;
Schreiber, OM ;
Walter, K ;
Rieh, JS ;
Jagannathan, B ;
Joseph, A ;
Subbanna, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (09) :1106-1114
[5]  
GRAY PR, 2001, ANAL DESIGN ANALOG I, P255
[6]  
JOHNSON EO, 1965, RCA REV, V26, P163
[7]   COLLECTOR BASE JUNCTION AVALANCHE EFFECTS IN ADVANCED DOUBLE-POLY SELF-ALIGNED BIPOLAR-TRANSISTORS [J].
LU, PF ;
CHEN, TC .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (06) :1182-1188
[8]   Reevaluation of the ftBVceo limit on Si bipolar transistors [J].
Ng, KK ;
Frei, MR ;
King, CA .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (08) :1854-1855
[9]  
PAASSCHENS JCJ, 2002, 2002806 NLUR PHIL RE
[10]   QUBiC3:: A 0.5μm BiCMOS production technology, with fT=30GHz, fmax=60GHz and high-quality passive components for wireless telecommunication applications [J].
Pruijmboom, A ;
Szmyd, D ;
Brock, R ;
Wall, R ;
Morris, N ;
Fong, K ;
Jovenin, F .
PROCEEDINGS OF THE 1998 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 1998, :120-123