Design of adaptive MC-CDMA receiver using low power parallel-pipelined FFT architecture

A design of multicarrier code division multiple access (MC-CDMA) receiver is proposed in this paper with novel low power parallel-pipelined FFT. The receiver is constructed based on number of sub-carrier systems which include two FFT blocks for demodulation, combiners for dispreading and equalizing the FFT outputs to recover the transmitted signals, and Viterbi decoder. The FFT architecture is constructed based on parallel-pipelined technique which includes different combination of hybrid low power techniques such as parallel-pipelined architectures, multiplier-less units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and low power butterfly architecture. Clock gating is extensively used in combiner to reduce power consumption by disabling the clock for the inactive circuits in FFT architecture. Viterbi decoder is implemented using trace back technique. It reduces the total power consumption to a considerable amount. By utilizing all the above techniques the design of proposed MC-CDMA receiver is implemented with Verilog HDL and synthesized in Cadence design tool using TSMC 0.18 mu m technology file. The result shows the overall power reduction about 48%, area reduction 23%.