A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA

被引：10

作者：

Bagheriye, Leila ^{[1
]}

Toofan, Siroos ^{[1
]}

Saeidi, Roghayeh ^{[2
]}

Zeinali, Behzad ^{[3
]}

Moradi, Farshad ^{[3
]}

机构：

[1] Univ Zanjan, Dept Elect Engn, Zanjan 45195313, Iran

[2] Iran Telecommun Res Ctr, ICT Secur, Tehran 141553961, Iran

[3] Aarhus Univ, Dept Engn, DK-8200 Aarhus, Denmark

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2018年 / 65卷 / 11期

关键词：

Low power; nonvolatile SRAM (NV-SRAM); spin-transfer-torque (STT); magnetic resistive random-access memory (MRAM); field programmable gate array (FPGA);

D O I：

10.1109/TCSII.2017.2768409

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, a novel low-power, low-area nonvolatile (NV) static random access memory (SRAM) that uses a single magnetic tunneling junction for store/restore operation is proposed. The proposed cell is dynamically reconfigurable in the background, which makes it a proper alternative to replace the SRAM cells of conventional field-programmable gate arrays (FPGAs) for the development of NV-FPGAs. The simulation results show that the proposed cell offers 8.8x lower store time, 1.52x (1.08x) lower store-0 (store-1) energy, and 3.54x lower restore energy, in comparison with the recently reported work. In addition, a high loading speed of 1 ns is achieved by using a separately supplied initialization and pulsed overwrite schemes.

引用

页码：1708 / 1712

页数：5

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