A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS

被引：0

作者：

Chung, Yung-Hui ^{[1
]}

Lin, Yi-Shen ^{[1
]}

Zeng, Qi-Feng ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, 43,Keelung Rd,Sec 4, Taipei 10607, Taiwan

来源：

2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018) | 2018年

关键词：

Analog-to-digital conversion (ADC); digital-to-analog conversion (DAC); successive-approximation; SAR; window switching;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 12-bit 20-MS/s SAR ADC incorporating the window-switching technique. The proposed fast-binary-window DAC switching scheme can effectively remove the major capacitor-DAC transition error to improve the DAC linearity and suppress DAC switching errors to improve the SNR. To maintain a good production yield, a dual-reference capacitor-DAC is applied to have a small total capacitance. The ADC was implemented in 180nm CMOS. It consumes 1.22 mW from a 1.5-V supply. The measured peak SNDR and SFDR are 61.9 and 81 dB, respectively. The peak ENOB is 10 bits, equivalent to a peak FOM of 59.6 fJ/conversion-step.

引用

页码：34 / 37

页数：4

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