Design considerations and strategies for high-reliable STT-MRAM

被引：107
作者：
Zhao, W. S. [1 ,2 ]
Devolder, T. [1 ,2 ]
Lakys, Y. [1 ,2 ]
Klein, J. O. [1 ,2 ]
Chappert, C. [1 ,2 ]
Mazoyer, P. [3 ]
机构：
[1] Univ Paris 11, IEF, F-91405 Orsay, France
[2] CNRS, UMR8622, F-91405 Orsay, France
[3] STMicroelectronics, F-38026 Grenoble, France
来源：
MICROELECTRONICS RELIABILITY | 2011年 / 51卷 / 9-11期
关键词：
D O I：
10.1016/j.microrel.2011.07.001
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Benefiting from Spin Transfer Torque (STT) switching approach, second generation of Magnetic RAM (MRAM) promises low power, great miniaturization prospective (<22 nm) and easy integration with CMOS process. It becomes actually a strong non-volatile memory candidate for both embedded and standalone applications. However STT-MRAM suffers from important reliability issues compared with the conventional one based on magnetic field switching, for example, a read-current could write erroneously the stored data, the low Resistance Area (RA) value drives high sensing error rate. This paper presents the considerations and strategies from design point of view for the reliability enhancement. Mixed transient and statistical simulations have been performed by using a STT-MRAM compact model and CMOS 65 nm design kit. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1454 / 1458
页数：5
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