Modeling of Processor Datapaths with VLIW Architecture at the System Level

The article discusses an approach to designing a datapath for a processor with a VLIW architecture. A feature of this architecture is the ability to implement an arithmetic-logic device with a complex structure, which leads to an explosive growth of possible options. The choice of the best option is complicated by conflicting requirements for the functionality and characteristics of the topological implementation of the processor. The article discusses the application of modeling at the transaction level to assess the characteristics of the processor when performing model tasks, followed by a description of the resulting solution at the RTL level. To describe the structure of the arithmetic-logical unit, a modification of the known description is proposed with the help of four parameters characterizing the number of operations, operands and latency in the datapath. The proposed modification makes it possible to describe asymmetric datapaths as part of an arithmetic-logic device with a complex structure. A consistent description of the high-level programming model and the register transfer layer allows for reduced design time and allows for joint design of hardware and support tools.