Low-power multiplier designs using dual supply voltage technique

A tree multiplier design approach based on dual voltage supply technique is proposed. The design consists of two types of full-adder units, one with a higher voltage supply (3.3V) and the other at lower voltage (2.5V). The 3.3V full-adder units are used exclusively in the most critical path of the multiplier to guarantee its best overall performance while the 2.5V units are used in the region where the timing is not critical to reduce the power consumption. To ensure that the performance of the multiplier is maintained, the slower 2.5V adder units are systematically replaced by the faster 3.3V adders in the violating paths to bring the timing to be within the limit. Our technique is verified through actual layout and found to be able to reduce power consumption of the tree multiplier up to 42% in the 16x16-bit multiplier without deteriorating its delay performance.