A Low-Overhead FFT Design With Higher SEU Resilience Implemented in FPGA

被引：7

作者：

Wang, H. -B. ^{[1
,2
]}

Wang, Y. -S. ^{[1
]}

Cui, J. -L. ^{[1
]}

Wang, S. -L. ^{[3
]}

Liang, T. -J. ^{[3
]}

Mei, B. ^{[4
]}

Liu, X. -F. ^{[1
]}

Qian, R. ^{[5
]}

机构：

[1] Hohai Univ, Coll IoT Engn, Changzhou 213022, Jiangsu, Peoples R China

[2] Chinese Res Inst Atom Energy Sci, Innovat Fdn Radiat Applicat, Beijing 102413, Peoples R China

[3] Chinese Acad Sci, Inst High Energy Phys, Dongguan 523000, Peoples R China

[4] China Acad Space Technol, Beijing 100094, Peoples R China

[5] Jiangsu Jotry Elect Technol Co Ltd, Changzhou 213100, Jiangsu, Peoples R China

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2020年 / 67卷 / 05期

关键词：

Fast Fourier transform (FFT); fault injection; field programmable gate array (FPGA); neutron exposure; single-event upset (SEU); soft error rate (SER); ERROR-DETECTION; RELIABILITY; RADIATION;

D O I：

10.1109/TNS.2020.2984848

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For area and power constraint applications in mission critical systems, the traditional fast Fourier transform (FFT) design requires huge hardware resources for data processing. In this article, we, therefore, present a low-overhead radix-2 FFT design that reduces hardware resources by simplifying the first two stages of the butterfly computations. Both the proposed design and the traditional design have been implemented in the MicroZus-20 (XC7Z020) platform. Their single-event performances have been compared through both fault injections and neutron exposure, and the experimental results demonstrate that the proposed design reduces the soft error rate by 53.8%. Also, the proposed FFT reduces the hardware resource consumption and circuit area by 64.8% when compared with the traditional design.

引用

页码：805 / 810

页数：6

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