A 10-bit binary-weighted DAC with digital background LMS calibration

被引：8
作者：
Shen, Ding-Lan [1 ,2 ]
Lai, Yuan-Chun [1 ,2 ]
Lee, Tai-Cheng [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2007年
关键词：
binary-weighted DAC; LMS calibration;
D O I：
10.1109/ASSCC.2007.4425703
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm(2) in a 0.18-mu m CMOS technology and consumes 27 mW from a 1.8-V supply.
引用
收藏
页码：352 / +
页数：2
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