A 10-b 80Ms/s time-interleaved pipeline ADC using partially opamp sharing scheme

被引：0
|
作者：
Cao Junmin [1 ]
Chen Zhongjian [1 ]
Lu Wengao [1 ]
Zhao Baoying [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/ICASIC.2007.4415616
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10-bit 80MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5um technology, the ADC dissipates 210mw of power from a 5v supply, and achieves a peak SNDR of 56dB at 80Ms/s.
引用
收藏
页码：257 / 260
页数：4
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