A Novel Test Strategy and Fault-Tolerant Routing Algorithm for NoC Routers

被引:0
作者
Alamian, Sanaz Sadat [1 ]
Fallahzadeh, Ramin [1 ]
Hessabi, Shaahin [1 ]
Alirezaie, Javad [2 ]
机构
[1] Sharif Univ Technol, Dept Comp Engn, Tehran, Iran
[2] Ryerson Univ, Dept Elect & Comp Engn, Toronto, ON, Canada
来源
2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013) | 2013年
关键词
NoC Routers; Fault-tolerant NoC; Functional Test; Routing Algorithm; Latency;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we present a novel routing algorithm in order to avoid deadlock and packet dropping. In our proposed algorithm the network-on-chip (NoC) is capable of tolerating faults in presence of control faults in combinational parts of routers. In addition, by modifying the functionality of the router, the router is enabled to test its own, as well as the preceding router's functionality based on the routing algorithm, destination address and previous router's situation. Each router recognizes the faulty neighbor and announces it to successive routers. In this scheme no extra packets will be generated. We analyze the effects of our method on latency, power consumption and drop rate. Our experimental results illustrate that, fault coverage for routers can reach up to 100% with yet low power consumption and significant improvement in latency compared to the baseline approach.
引用
收藏
页码:133 / +
页数:2
相关论文
共 17 条
[1]  
Alaghi A., 2007, 22 IEEE INT S DEF FA
[2]  
Alhussien A., 2012, 25 IEEE INT CIRC SYS
[3]  
Amory A. M., 2005, INT TEST C ITC
[4]  
[Anonymous], WORLD APPL SCI J
[5]  
[Anonymous], 2010, 11 LAT AM TEST WORKS
[6]   A Reliable Routing Architecture and Algorithm for NoCs [J].
DeOrio, Andrew ;
Fick, David ;
Bertacco, Valeria ;
Sylvester, Dennis ;
Blaauw, David ;
Hu, Jin ;
Chen, Gregory .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (05) :726-739
[7]  
Grecu C., 2006, Proc. IEEE Int'l On-Line Testing Symp. (IOLTS '06), P145
[8]   BIST for network-on-chip interconnect infrastructures [J].
Grecu, Cristian ;
Pande, Partha ;
Ivanov, Andre ;
Saleh, Res .
24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2006, :30-+
[9]  
Hosseinabady M, 2007, DES AUT TEST EUROPE, P361
[10]  
Hosseinabady M, 2006, DES AUT TEST EUROPE, P1171