Low Voltage Error Resilient SRAM using Run-time Error Detection and Correction

被引：0

作者：

Kumar, Ashish ^{[1
]}

Visweswaran, G. S. ^{[2
]}

Saha, Kaushik ^{[2
]}

机构：

[1] STMicroelect Pvt Ltd, Greater Noida, India

[2] Indian Inst Technol, Delhi, India

来源：

ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC) | 2015年

关键词：

CMOS memory circuits; error resilience; redundancy; SRAM; Static noise margin; write margin; low voltage memory; dynamic recovery;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An adaptive SRAM architecture that can dynamically detect and correct read and write failures is discussed. The proposed method detects the failures, extends the failing cycles and subsequently corrects those. Data in the failing clock cycle are discarded and are made available in the subsequent cycle, if the failure is corrected. To detect write failures an adaptive write technique based on dummy write column is used. While for the read failures, the proposed read technique uses two non-identical sense amplifiers. We could achieve a Vmin lowering of 180mV for a 90nm ultra low power, high density 6T CMOS SRAM with less than 0.1 percent impact on throughput. This has been achieved without using assist-circuits or ECC. Area overhead is 3 percent for a 128Kb memory instance.

引用

页码：335 / 338

页数：4