A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

被引：15

作者：

Jagar, S ^{[1
]}

Cheng, CF ^{[1
]}

Zhang, SD ^{[1
]}

Wang, HM ^{[1
]}

Poon, MC ^{[1
]}

Kok, CW ^{[1
]}

Chan, MS ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2003年 / 50卷 / 04期

关键词：

BSIM and SPICE; GBs; MILC; polysilicon; TFT modeling and circuit simulation; thin-film transistors;

D O I：

10.1109/TED.2003.812487

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension., The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.

引用

页码：1103 / 1108

页数：6

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