RF CMOS on high-resistivity substrates for system-on-chip applications

被引：67

作者：

Benaissa, K ^{[1
]}

Yang, JY ^{[1
]}

Crenshaw, D ^{[1
]}

Williams, B ^{[1
]}

Sridhar, S ^{[1
]}

Ai, J ^{[1
]}

Boselli, G ^{[1
]}

Zhao, S ^{[1
]}

Tang, SP ^{[1
]}

Ashburn, S ^{[1
]}

Madhani, P ^{[1
]}

Blythe, T ^{[1
]}

Mahalingam, N ^{[1
]}

Shichijo, H ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2003年 / 50卷 / 03期

关键词：

D O I：

10.1109/TED.2003.810470

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The use of high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SOC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation., We also discuss the integration issues including latch-up and well-well isolation in a 0.35-mum Cu metal pitch, 0.1-mum-gate-length RF CMOS technology.

引用

页码：567 / 576

页数：10

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[11] S-PARAMETER-BASED IC INTERCONNECT TRANSMISSION-LINE CHARACTERIZATION [J].