Modeling the function cache for worst-case execution time analysis

被引：3

作者：

Kirner, Raimund ^{[1
]}

Schoeberl, Martin ^{[2
]}

机构：

[1] Vienna Univ Technol, Inst Tech Informat, Real Time Syst Grp, A-1060 Vienna, Austria

[2] Vienna Univ Technol, Inst Tech Informat, Sistem Chip Grp, A-1060 Vienna, Austria

来源：

2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2007年

基金：

奥地利科学基金会;

关键词：

worst-case execution time; WCET; cache analysis; function cache;

D O I：

10.1109/DAC.2007.375211

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function caches, a special kind of instruction cache that caches whole functions only. This cache was designed with the aim to be more predictable for the worst-case than existing instruction caches. Within this paper we developed a cache analysis technique for the function cache. One of the new concepts of this analysis technique is the local persistence analysis, which allows to precisely model the function cache.

引用

页码：471 / +

页数：3

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