FPGA implementation of digital PID

被引：0

作者：

Rezaee, A ^{[1
]}

机构：

[1] Amirkabir Univ Technol, Tehran, Iran

来源：

Proceedings of the 7th WSEAS International Conference on Automatic Control, Modeling and Simulation | 2005年

关键词：

control; PID; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper concerns the design of an ASIC with FPGA technology. The ASIC function is the PID controller The design focus on optimization of a silicon area and speed operation. This ASIC-PID has been implemented by means of three blocks: Adder, Multiplier and control unit. The speed performance of this system is compared to design with Digital PID on AVR (AT mega 128L).This hardware implementation can be done in three different architectures: Serial, Parallel or Mixed. In all cases this kind of electronic implementation is very fast response than a software.

引用

页码：348 / 352

页数：5