Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems

被引：2

作者：

Cardoso, Joao M. P. ^{[1
,2
]}

DeHon, Andre ^{[3
]}

Pozzi, Laura ^{[4
]}

机构：

[1] Univ Porto, Dept Informat Engn, Fac Engn, P-4099002 Porto, Portugal

[2] Inst Syst & Comp Engn Technol & Sci, P-4200465 Porto, Portugal

[3] Univ Penn, Elect & Syst Engn Dept, Philadelphia, PA 19104 USA

[4] Univ Svizzera Italiana, Fac Informat, CH-6900 Lugano, Switzerland

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2021年 / 70卷 / 12期

关键词：

Special issues and sections; Field programmable gate arrays; Program processors; Predictive models; Reconfigurable architectures;

D O I：

10.1109/TC.2021.3117316

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The papers in this special section focus on compiler optimization for FPGA-based systems. Reconfigurable computing (RC) is growing in importance in many computing domains and systems, from embedded, mobile to cloud, and high-performance computing. We have witnessed important advancements regarding the programming of RC-based systems, but further improvements are needed, especially regarding efficient techniques for automatic mapping of computations described in high-level languages to the RC resources. The resources of high-end FPGAs allow these devices to implement complex Systemson-a-Chip (SoCs) and substantial computational components of software applications, e.g., when used as hardware accelerators and/or as more energy-efficient computing platforms. This, however, increases the continuous need for efficient compilers targeting FPGAs, and other RC platforms, from high-level programming languages.

引用

页码：2013 / 2014

页数：2