W-Band Direct-Modulation >20-Gb/s Transmit and Receive Building Blocks in 32-nm SOI CMOS

This paper presents Gb/s-speed circuit building blocks in 32-nm CMOS SOI, for a >20-Gb/s Cartesian direct-modulation W-band transmitter. Transmitter systems non-idealities and performance limitations are discussed, and circuit design techniques and analyses are presented. The transmitter employs two 2-b high-speed RF digital-to-analog converters driven in quadrature, 20-dB gain W-band LO drivers, and 30-Gb/s high-speed digital retimers and deserializers, and is capable of supporting BPSK/PAM4/QPSK/16-QAM modulation schemes, at a saturated output power P-sat of +4 dBm. A maximum data rate of 20 Gb/s was achieved when operating in QPSK mode, 4 Gb/s in 16-QAM mode, and 12 Gb/s in both BPSK and PAM4 modes. The chip occupies 1.4x0.8 mm(2), and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK and 16-QAM modes, resulting in the state-of-the-art 9-, 11-, and 55-pJ/b peak efficiencies, respectively. A mixer-first wideband W-band receiver that includes a passive mixer and a wideband transimpedance amplifier is also presented. Measurements of the receiver chip demonstrated its capability to downconvert and amplify highly complex modulated waveforms (>256-QAM), and at high data rates, up to 60 Gb/s in 64-QAM, which proves the feasibility of building high dynamicrange mm-wave receivers with bandwidth greater than 30 GHz. The receiver chip was also built in 32-nm CMOS SOI, occupying a core area of 0.18x0.1 mm(2).