High-speed CMOS Track/Hold circuit design

被引：0
|
作者：
Kobayashi, H
Zin, MAM
Kobayashi, K
San, H
Sato, H
Ichimura, JI
Onaya, Y
Kurosawa, N
Kimura, Y
Yuminaka, Y
Tanaka, K
Myono, T
Abe, F
机构：
[1] Gunma Univ, Dept Elect Engn, Kiryu, Gumma 3768515, Japan
[2] Sanyo Elect Corp, Semicond Co, Oizumi, Gunma 3700596, Japan
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2001年 / 27卷 / 1-2期
关键词：
Track/Hold circuit; Sample/Hold circuit; AD converter; sampling; CMOS;
D O I：
10.1023/A:1011283613869
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the design of a high-speed CMOS Track/Hold circuit in front of an ADC. The Track/Hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 mum CMOS BSIM3v3 parameters showed that it achieves a signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption.
引用
收藏
页码：161 / 170
页数：10
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