共 11 条
- [1] STELLAR: Energy-Efficient and Low-Latency SNN Algorithm and Hardware Co-design with Spatiotemporal Computation 2024 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, HPCA 2024, 2024, : 172 - 185
- [2] Algorithm-hardware co-design for Energy-Efficient A/D conversion in ReRAM-based accelerators 2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2024,
- [3] Scalable Energy-Efficient, Low-Latency Implementations of Trained Spiking Deep Belief Networks on SpiNNaker 2015 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2015,
- [6] Reinforcement co-Learning of Deep and Spiking Neural Networks for Energy-Efficient Mapless Navigation with Neuromorphic Hardware 2020 IEEE/RSJ INTERNATIONAL CONFERENCE ON INTELLIGENT ROBOTS AND SYSTEMS (IROS), 2020, : 6090 - 6097
- [7] IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning PROCEEDINGS OF THE 32ND GREAT LAKES SYMPOSIUM ON VLSI 2022, GLSVLSI 2022, 2022, : 373 - 377
- [8] Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition 2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 129 - 130
- [10] Hyperdimensional Computing with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language Recognition 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,