Noise-tolerant design and analysis for a low-voltage dynamic full adder cell

In an attempt to study the behavior of dynamic circuits in the presence of deep submicron noise when operating at a low supply voltage, this paper presents noise tolerant design and analysis for an enhanced dynamic full adder cell based on the NORA-CMOS logic style. The noise tolerance capability is achieved by applying the twin-transistor technique on both the P and the N parts of the circuit. A prototype is constructed for both the standard and the designed noise tolerant circuits using 0.18 CMOS technology and simulated using Hspice at supply voltage ranges from 0.9v to 2.7v. Noise immunity curves are developed and used to calculate the Average Noise Threshold Energy which shows a 2.5 times improvement when compared with the conventional design. The noise enhancement comes at the expense of 2.1 times extra power consumption.