An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware

被引：0

作者：

Mesquita, Daniel ^{[1
]}

Perin, Guilherme ^{[1
]}

Herrmann, Fernando Luis ^{[1
]}

Martins, Joao Baptista ^{[1
]}

机构：

[1] Univ Fed Uberlandia, FACOM, Uberlandia, MG, Brazil

来源：

SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2010年

关键词：

Cryptography; Modular Exponentiation; FPGA; EXPONENTIATION; MULTIPLICATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an efficient architecture to perform modular exponentiation using the Montgomery Powering Ladder algorithm The implementation is composed by two parallel modular multiplication modules in order to speed-up the modular exponentiation time. The modular multiplication architecture is high-radix and presents an one-dimensional array of processing elements within multiplexed multipliers. This architecture can performs the 1024 bits RSA decryption in 2.5 ms. Furthermore, the modular exponentiation architecture presents a countermeasure against SPA attack.

引用

页码：121 / 126

页数：6

共 50 条

[31] Fast and Efficient Hardware Implementation of HQC
Deshpande, Sanjay
Xu, Chuanqi
Nawan, Mamuri
Nawaz, Kashif
Szefer, Jakub
SELECTED AREAS IN CRYPTOGRAPHY - SAC 2023, 2024, 14201 : 297 - 321
[32] Efficient VLSI Implementation for Montgomery Multiplication in GF(2(m))
Chiou, Che-Wun
Lee, Chiou-Yng
Deng, An-Wen
Lin, Jim-Min
JOURNAL OF APPLIED SCIENCE AND ENGINEERING, 2006, 9 (04): : 365 - 372
[33] A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator
Ananthan, T.
Vaidyan, M. V.
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2013, 6 (04)
[34] FPGA Implementation of An Efficient Montgomery Multiplier For Adaptive Filtering Application
Mulla, Nahed
Kasetwar, Abhay
2014 INTERNATIONAL CONFERENCE ON POWER, AUTOMATION AND COMMUNICATION (INPAC), 2014, : 66 - 70
[35] Lattice-Based Signatures: Optimization and Implementation on Reconfigurable Hardware
Gueneysu, Tim
Lyubashevsky, Vadim
Poeppelmann, Thomas
IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (07) : 1954 - 1967
[36] Efficient FPGA implementation of modular multiplication based on Montgomery algorithm
Yang, Yatao
Wu, Chao
Li, Zichen
Yang, Junming
MICROPROCESSORS AND MICROSYSTEMS, 2016, 47 : 209 - 215
[37] Implementation of an Edge Detection Algorithm using FPGA Reconfigurable Hardware
Abed, Sa'ed
JOURNAL OF ENGINEERING RESEARCH, 2020, 8 (01): : 179 - 197
[38] Design of a Nonhomogeneous Nonlinear Synchronizer and Its Implementation in Reconfigurable Hardware
Pulido-Luna, Jesus R.
Lopez-Renteria, Jorge A.
Cazarez-Castro, Nohe R.
MATHEMATICAL AND COMPUTATIONAL APPLICATIONS, 2020, 25 (03)
[39] Hardware/software design implementation of feature detection for a reconfigurable processor
Dang, PP
Chau, PM
VISUAL COMMUNICATIONS AND IMAGE PROCESSING '99, PARTS 1-2, 1998, 3653 : 758 - 766
[40] Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier
Ors, Berna
Batina, Lejla
Preneel, Bart
Vandewalle, Joos
INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS, 2008, 3 (04) : 229 - 240

← 1 2 3 4 5 →