An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware

被引：0

作者：

Mesquita, Daniel ^{[1
]}

Perin, Guilherme ^{[1
]}

Herrmann, Fernando Luis ^{[1
]}

Martins, Joao Baptista ^{[1
]}

机构：

[1] Univ Fed Uberlandia, FACOM, Uberlandia, MG, Brazil

来源：

SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2010年

关键词：

Cryptography; Modular Exponentiation; FPGA; EXPONENTIATION; MULTIPLICATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an efficient architecture to perform modular exponentiation using the Montgomery Powering Ladder algorithm The implementation is composed by two parallel modular multiplication modules in order to speed-up the modular exponentiation time. The modular multiplication architecture is high-radix and presents an one-dimensional array of processing elements within multiplexed multipliers. This architecture can performs the 1024 bits RSA decryption in 2.5 ms. Furthermore, the modular exponentiation architecture presents a countermeasure against SPA attack.

引用

页码：121 / 126

页数：6