An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware

被引：0

作者：

Mesquita, Daniel ^{[1
]}

Perin, Guilherme ^{[1
]}

Herrmann, Fernando Luis ^{[1
]}

Martins, Joao Baptista ^{[1
]}

机构：

[1] Univ Fed Uberlandia, FACOM, Uberlandia, MG, Brazil

来源：

SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2010年

关键词：

Cryptography; Modular Exponentiation; FPGA; EXPONENTIATION; MULTIPLICATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an efficient architecture to perform modular exponentiation using the Montgomery Powering Ladder algorithm The implementation is composed by two parallel modular multiplication modules in order to speed-up the modular exponentiation time. The modular multiplication architecture is high-radix and presents an one-dimensional array of processing elements within multiplexed multipliers. This architecture can performs the 1024 bits RSA decryption in 2.5 ms. Furthermore, the modular exponentiation architecture presents a countermeasure against SPA attack.

引用

页码：121 / 126

页数：6

共 21 条

[1] Scalable hardware implementing high-radix Montgomery multiplication algorithm [J].

Bernard, F. .

JOURNAL OF SYSTEMS ARCHITECTURE, 2007, 53 (2-3) :117-126

[2] Montgomery modular exponentiation on reconfigurable hardware [J].

Blum, T ;

Paar, C .

14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, :70-77

[3]

HARRIS MAS, 2005, P ARITH 05 MASS US I, P172

[4]

Joye M, 2002, LECT NOTES COMPUT SC, V2523, P291

[5]

KNUTH DE, 1951, ART COMPUTER PROGRAM, V2

[6]

LAUE FRS, 2008, P VLSI 08 IEEE COMP, P87

[7] High-radix systolic modular multiplication on reconfigurable hardware [J].

McIvor, C ;

McLoone, M ;

McCanny, JV .

FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2005, :13-18

[8]

MCIVOR MMC, 2004, P FCCM 04 IEEE COMP, P279

[9]

Menezes AJ., 2001, HDB APPL CRYPTOGRAPH

[10]

MESQUITA LTG, 2006, P FPL 06 IEEE COMP S

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