A novel structure for digital image stabilizer

被引：10

作者：

Chen, GR ^{[1
]}

Yeh, YM ^{[1
]}

Wang, SJ ^{[1
]}

Chiang, HC ^{[1
]}

机构：

[1] OES ITRI, Hsinchu 310, Taiwan

来源：

2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS | 2000年

关键词：

D O I：

10.1109/APCCAS.2000.913416

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.

引用

页码：101 / 104

页数：4