Characterization of Radiation-Induced SRAM and Logic Soft Errors from 0.33V to 1.0V in 65nm CMOS

被引：0

作者：

Pawlowski, Robert ^{[1
]}

Crop, Joseph ^{[1
]}

Cho, Minki ^{[2
]}

Tschanz, James ^{[2
]}

De, Vivek ^{[2
]}

Fairbanks, Thomas ^{[3
]}

Quinn, Heather ^{[3
]}

Borkar, Shekhar ^{[2
]}

Chiang, Patrick Yin ^{[1
]}

机构：

[1] Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA

[2] Intel Corp, Hillsboro, OR USA

[3] Alamos Natl Lab, Los Alamos, NM USA

来源：

2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2014年

关键词：

logic; memory; near-threshold; reliability; soft errors;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low V-DD. Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when V-DD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low V-DD.

引用

页数：4

共 14 条

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