A design for modular exponentiation coprocessor in mobile telecommunication terminals

被引：0

作者：

Kato, T ^{[1
]}

Ito, S ^{[1
]}

Anzai, J ^{[1
]}

Matsuzaki, N ^{[1
]}

机构：

[1] Adv Mobile Telecommun Secur Technol Res Labs Co L, Kohoku Ku, Yokohama, Kanagawa 2220033, Japan

来源：

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS-CHES 2000, PROCEEDINGS | 2001年 / 1965卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Following requirements are necessary when implementing public key cryptography in a mobile telecommunication terminal. (1) simultaneous highspeed double modular exponentiation calculation, (2) small size and low power consumption, (3) resistance to side channel attacks, We have developed a coprocessor that provides these requirements. In this coprocessor, right-to-left binary exponentiation algorithm was extended for double modular exponentiations by designing new circuit configuration and new schedule control methods. We specified the desired power consumption of the circuit at the initial design stage. Our proposed method resists side channel attacks that extract secret exponent by analyzing the target's power consumption and calculation time.

引用

页码：216 / 228

页数：13

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