A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

被引：83

作者：

Kim, Jisu ^{[1
]}

Ryu, Kyungho ^{[1
]}

Kang, Seung H. ^{[2
]}

Jung, Seong-Ook ^{[1
]}

机构：

[1] Yonsei Univ, Sch Elect & Elect Engn, Seoul 120749, South Korea

[2] Qualcomm Inc, San Diego, CA 92121 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2012年 / 20卷 / 01期

关键词：

Balancing; read disturbance; sensing circuit; sensing margin; source degeneration; STT-MRAM; DESIGN; YIELD; RAM;

D O I：

10.1109/TVLSI.2010.2088143

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme. Monte Carlo HSPICE simulation results using 65 nm technology model parameters show that the proposed sensing circuit achieves an read access yield of 96.3% with a sensing current of 43.1 uA at a supply voltage of 1.1 V for 32 M bit, whereas the conventional sensing circuit achieves an read access yield of only 0% (81.5%) with a sensing current of 48.0 uA (64.2 uA) at a supply voltage of 1.1 V (1.6 V).

引用

页码：181 / 186

页数：7

共 11 条

[1] A high-speed 128-kb MRAM core for future universal memory applications [J].

DeBrosse, J ;

Gogl, D ;

Bette, A ;

Hoenigschmid, H ;

Robertazzi, R ;

Arndt, C ;

Braun, D ;

Casarotto, D ;

Havreluk, R ;

Lammers, S ;

Obermaier, W ;

Reohr, WR ;

Viehmann, H ;

Gallagher, WJ ;

Müller, G .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (04) :678-683

[2] A 16-Mb MRAM featuring bootstrapped write drivers [J].

Gogl, D ;

Arndt, C ;

Barwin, JC ;

Bette, A ;

DeBrosse, J ;

Gow, E ;

Hoenigschmid, H ;

Lammers, S ;

Lamorey, M ;

Lu, Y ;

Maffitt, T ;

Maloney, K ;

Obermaier, W ;

Sturm, A ;

Viehmann, H ;

Willmott, D ;

Wood, M ;

Gallagher, WJ ;

Mueller, G ;

Sitaram, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) :902-908

[3]

Hosomi M, 2005, INT EL DEVICES MEET, P473

[4]

Jeong G., 2003, P IEEE INT SOL STAT, P128

[5] SPRAM (SPin-transfer torque RAM) design and its impact on digital systems [J].

Kawahara, T. ;

Takemura, R. ;

Takahashi, H. ;

Ohno, H. .

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, :1011-+

[6] 2 Mb SPRAM (SPin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read [J].

Kawahara, Takayuki ;

Takemura, Riichiro ;

Miura, Katsuya ;

Hayakawa, Jun ;

Ikeda, Shoji ;

Lee, Young Min ;

Sasaki, Ryutaro ;

Goto, Yasushi ;

Ito, Kenchi ;

Meguro, Toshiyasu ;

Matsukura, Fumihiro ;

Takahashi, Hiromasa ;

Matsuoka, Hideyuki ;

Ohno, Hideo .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (01) :109-120

[7] A perpendicular spin torque switching based MRAM for the 28 nm technology node [J].

Klostermann, U. K. ;

Angerbauer, A. ;

Gruening, U. ;

Kreupl, F. ;

Ruehrig, M. ;

Dahmani, F. ;

Kund, M. ;

Mueller, G. .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :187-+

[8] A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion [J].

Miura, K. ;

Kawahara, I. ;

Takemura, R. ;

Hayakawa, J. ;

Ikeda, S. ;

Sasaki, R. ;

Takahashi, H. ;

Matsuoka, H. ;

Ohno, H. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :234-+

[9] Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation [J].

Nho, Hyunwoo ;

Yoon, Sei-Seung ;

Wong, S. Simon ;

Jung, Seong-Ook .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2008, 55 (09) :907-911

[10]

Rizzo N., 2010, P NONVOL MEM WORKSH

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