Bilateral 60-V Amorphous InGaZnO Thin-Film Transistors With Symmetric Stair Gate Dielectric

This work implemented bilateral 60-V amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with symmetric stair gate dielectric at the contact sides. The stair gate dielectric lowers the electrical field between the gate and the contacts, enhancing the breakdown voltage (V-BD). The V-BD was improved from sub-20 to 60 V and a bilateral VBD of 60 V was achieved at the total stair length (L-stair) of over 2.9 f m for the proposed device. The transconductance (G(m)) degrades with the increasing L-stair, attributed to the rising equivalent thickness of the stair gate dielectric. The gate-four-probe (GFP) method measurements reveal that the ON-resistance (RoN) of the stair gate region has a linear dependence on the L-stair. The increasing electron concentration in the channel outside the stair region optimizes the output current, as confirmed by the TCAD simulation. The breakdown properties of the devices with a small L-stair ( < 0.1 mu m) were also simulated. The proposed symmetric stair gate dielectric a-IGZO TFTs possessed low R-ON and high VBD at the same time.