Hardware - Software codesign for matrix multiplication

A codesign is the simultaneous design of hardware and software subsystems. In our codesign, we exploit the highly parallel nature of matrix multiplication which cannot be exploited in our purely software implementation. The hardware part of our codesign system is responsible for performing the arithmetic operations. This includes the matrix multiplier, which performs concurrent multiplication and addition operations of matrix multiplication. Our matrix multiplier is modeled in VHDL and runs on an ARC-PCI FPGA board. The purpose of the software part of our codesign system is to provide I/O to the hardware. This part is implemented on a PC with a C program and a device driver to communicate with the board. We present the performance comparison of our codesign and purely software implementation, as well as the performance comparison of existing parallel implementations. Examples of applications that require large, fast matrix multiplication are bipartite graph determination (nonexistence of odd cycles), Economics (Leontief input-output model), power-invariant transformations (power systems), Cryptography, and genetics modeling (Markov chains).