A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators
被引:0
作者:
Lao, CI
论文数: 0引用数: 0
h-index: 0
机构:
Univ Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R ChinaUniv Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R China
Lao, CI
[1
]
U, SP
论文数: 0引用数: 0
h-index: 0
机构:
Univ Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R ChinaUniv Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R China
U, SP
[1
]
Martins, RP
论文数: 0引用数: 0
h-index: 0
机构:
Univ Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R ChinaUniv Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R China
Martins, RP
[1
]
机构:
[1] Univ Macau, Analog & Mixed Signal VLSI Lab, Macau, Peoples R China
来源:
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
|
2005年
关键词:
D O I:
暂无
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
This paper presents a novel architecture for a high-order cascade oversampling modulator: semi-MASH based on the application of stage feedback within each stage and using appropriate error cancellation logic to spread the Noise Transfer Function (NTF) zero to extend the Signal-toQuantization Noise Ratio (SNQR). Moreover, minimum-noise-shaping-per-stage keeps 0dB overload region regardless of the stage number. An 8xOSR 5(th).order 1.5-bit semi-MASH design (1+1-1+1-1mb) will be presented as an example achieving 81 dB; Peak SNQR and 88 dB SFDR. More than 14 dB SNQR and 12 dB SFDR are gained by spreading the NTF zero. Behavioral simulations with MATLAB and SIMULINK demonstrate the good performance of the proposed architecture.