A new low-voltage full adder circuit

A new circuit based on combining XOR gates and double pass-transistor logic has been developed for implmenting a full adder. The main design objectives for these new circuits are low power consumption and full-voltage suing at a lour supply voltage. The proposed full adder circuit is compared with previously known circuits and is shown to provide superior performance. The new and previous full adder circuits have been fully simulated using HSPICE with 0.4 mu m CMOS technology at a 2.0V supply voltage. An extensive analysis of a 8-bit carry-select adder establishes the superiority of the proposed circuit in that application.