An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation

被引:2
|
作者
Ismail, Yasser [1 ]
Shaaban, Mohsen [1 ]
McNeely, Jason B. [1 ]
Bayoumi, Magdy A. [1 ]
机构
[1] Univ Louisiana Lafayette, Ctr Adv Comp Studies, Lafayette, LA 70504 USA
基金
美国国家科学基金会;
关键词
Adaptive search window size; discrete cosine transform (DCT)-manipulation; DCT phase correlation; fast motion estimation; frequency domain; SEARCH ALGORITHM; VIDEO;
D O I
10.1109/TVLSI.2010.2046686
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Motion estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Discrete cosine transform (DCT)-based phase correlation along with dynamic padding (DP) are the recently evolved frequency domain ME(FDME) techniques that promise to efficiently reduce the computational complexity of the ME process. DP uses dynamic padding thresholds to select the proper search area size according to a pre-estimated set of motion vectors (MVs). The main drawbacks of using conventional DP in the frequency domain are two-fold. First, the dynamic thresholds need to be estimated in the pixel (IDCT) domain which increases complexity. Second, the mismatched transformed search area is formed from different successive transformed blocks, which would lead to an inaccurate ME if the search area is not manipulated. In this paper, an efficient low complexity algorithm and high speed architecture are proposed to implement an adaptive manipulation unit engine (MUE). The MUE, the main module of the FDME system, adaptively decides the padding size and forges a matched transformed search area from the successive transformed blocks. Additionally, the proposed utilized dynamic thresholds are efficiently estimated in the frequency domain (FD). The MUE architecture is presented with two different design implementations trading off the VLSI design parameters. Implementation and simulation results project that the proposed MUE, when integrated in a whole FDME system, can perform ME for 60 fps of 4CIF video at 172 MHz.
引用
收藏
页码:1239 / 1248
页数:10
相关论文
共 50 条
  • [21] FPGA implementation of high speed parallel architecture for block motion estimation
    Rangarajan, P
    Prashanth, G
    Harish, PS
    2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS, 2004, : 245 - 250
  • [22] FREQUENCY DOMAIN: EFFICIENT AND HIGH SPEED TECHNOLOGY FOR VIDEO TRANSMISSION
    Ismail, Yasser
    El-etriby, Sherif
    Bayoumi, Magdy
    2011 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2011, : 278 - 282
  • [23] An efficient approach of fast motion estimation and compensation in wavelet domain video compression
    Cai, WT
    Adjouadi, M
    2004 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL II, PROCEEDINGS: SENSOR ARRAY AND MULTICHANNEL SIGNAL PROCESSING SIGNAL PROCESSING THEORY AND METHODS, 2004, : 977 - 980
  • [24] An efficient adaptive interpolation scheme for fast mesh-based motion estimation
    Mahdavi-Nasab, H.
    Kasaei, Shohreh
    2005 1st IEEE/IFIP International Conference in Central Asia on Internet (ICI), 2005, : 115 - 118
  • [25] An efficient VLSI architecture for H.264 variable block size motion estimation
    Ou, CM
    Le, CF
    Hwang, WJ
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2005, 51 (04) : 1291 - 1299
  • [26] An Efficient Motion Blurred Image Restoration Scheme based on Frequency Domain Estimation
    Yu, Ciao-Kai
    Tsai, Bing-Chen
    Hwang, Yin-Tsung
    2016 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-TAIWAN (ICCE-TW), 2016, : 61 - 62
  • [27] A High-Performance VLSI Architecture for Variable Block Size Motion Estimation
    Chi, Hsin-Chou
    Liu, Han-Sheng
    Tseng, Hsi-Che
    2014 IEEE 3RD GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE), 2014, : 123 - 124
  • [28] Scalable high-throughput variable block size motion estimation architecture
    Warrington, Stephen
    Chan, Wai-Yip
    Sudharsanan, Subramania
    MICROPROCESSORS AND MICROSYSTEMS, 2009, 33 (04) : 319 - 325
  • [30] Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard
    Hassen Loukil
    Abdulilah Mohammad Mayet
    Multimedia Tools and Applications, 2023, 82 : 46331 - 46349