An FPGA-based Hardware Accelerator for Simulating Spatiotemporal Neurons

被引：0

作者：

Tarawneh, Ghaith ^{[1
]}

Read, Jenny ^{[1
]}

机构：

[1] Newcastle Univ, Inst Neurosci, Framlington Pl, Newcastle Upon Tyne NE2 4HH, Tyne & Wear, England

来源：

2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2014年

关键词：

Hardware acceleration; Gabor filter; spatiotemporal neuron; motion detection; MOTION; IMPLEMENTATION; MODEL; MT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Simulating spatiotemporal neurons is fundamental to understanding motion detection mechanisms in the primary visual cortex and cloning these mechanisms in digital systems. We present a hardware accelerator that leverages the parallelism of a modern Field Programmable Gate Array ( FPGA) to increase the speed of spatiotemporal computations by 1 similar to 2 orders of magnitude for video framebuffer sizes up to 128x128x25 pixels. The accelerator is primarily intended for running simulations of large spatiotemporal neuron populations but can also be used in computer vision applications that require high-speed spatiotemporal processing such as realtime motion detection.

引用

页码：618 / 621

页数：4

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