4.2 Gbit/s single-chip FPGA implementation of AES algorithm

被引：25

作者：

Rodríguez-Henríquez, F ^{[1
]}

Saqib, NA ^{[1
]}

Díaz-Pérez, A ^{[1
]}

机构：

[1] IPN, CINVESTAV, Comp Sci Sect, Mexico City 07360, DF, Mexico

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 15期

关键词：

D O I：

10.1049/el:20030746

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high performance encryptor/decryptor core of the advanced encryption standard (AES) is presented. The proposed architecture is implemented on a single-chip FPGA using a fully pipelined approach. The results obtained show that this design offers up to 25.06% less area and yields up to 27.23% higher throughput than the fastest AES FPGA implementations reported to date.

引用

页码：1115 / 1116

页数：2