Nanometer MOSFET variation in minimum energy subthreshold circuits

被引：86

作者：

Verma, Naveen ^{[1
]}

Kwong, Joyce ^{[1
]}

Chandrakasan, Anantha P. ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 01期

基金：

加拿大自然科学与工程研究理事会;

关键词：

CMOS digital integrated circuits; leakage currents; logic design; low-power electronics; matching; static random access memory (SRAM); subthreshold; yield estimation;

D O I：

10.1109/TED.2007.911352

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-V-t circuits, but are plagued by increased variation and reduced I-ON/I-OFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metries are presented.

引用

页码：163 / 174

页数：12

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