Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Using 193nm lithography at NA=0.75, the minimum pitch that can be obtained in a single exposure is 160nm for dark field structures that are used in single damascene interconnect processing. In order to evaluate the critical electrical parameters for the smaller technologies, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm. Ibis corresponds to k1-factors of 0.27 to 0.19 for dense trenches. The designs have been split up into two layers at more relaxed pitch (twice the final pitch). The first step consists in patterning a small semi-isolated trench at this more relaxed pitch. Because of the limited resist resolution for semi-isolated trenches, shrink techniques such as resist reflow or RELACS are needed. After etching this first layer into a low-k material or metal hard mask, planarization of the topography is critical before performing the second exposure. The second exposure is then identical to the first one, but overlay to the first layer is extremely critical in order to get a reasonable process window. In this paper, we illustrate the feasibility of the double patterning technique for early sub-65nm-node evaluation of low-k materials. The resolution and processing limits will be shown for single layer resist processing with RELACS shrink for 193nm lithography at NA=0.75. The planarization for the second photo is done using organic BARC. We will also quantify the overlay requirements to measured and introduced overlay errors.