A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices

Through the age of nanoelectronics, device dimensions are curbed, and the size of transistors is rapidly reduced. Scaling down transistors results in high-speed switching, higher density, reduced power consumption, lower transistor costs. Some of the critical issues facing scaling down transistor sizes such as punch-through effect, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage roll-off, leakage current effects various proposed structure. The evolution of the semiconductor industry from the appropriate methods CMOS into a proposed structure called TFET. The TFET is a suitable method as a critical part of the power usage in circuit boards that achieves its target to meet reverse sub-threshold slope (SS) below the temperature limit (60 mV/dec in room temperature) with often a lower drive current implicitly than a MOSFET. In this study, an effort has been made to bring the roadmap of various TFET structures like Single gated TFET, Double gated TFET, Tri gated TFET, and, finally, Heterojunction TFET.