Efficient parallel finite field modular multiplier

被引：0
|
作者：
Li, H [1 ]
机构：
[1] Univ Lethbridge, Dept Math & Comp Sci, Lethbridge, AB T1K 3M4, Canada
来源：
ISPA 2003: PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS, PTS 1 AND 2 | 2003年
关键词：
finite field arithmetic; reconfigurable computing; all one polynomial; redundant canonical basis; VLSI; embedded systems; encryption;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, a redundant canonical basis representation with the irreducible All One Polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m+1)(2) 2-input AND gates and m(m+1) 2-input XOR gates. The time delay is T-AND + [log(2)(m + 1)]T-XOR. The proposed architectures are highly modular and well suited for high speed VLSI implementations.
引用
收藏
页码：434 / 437
页数：4
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