An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET

被引：21

作者：

Kaur, Harsupreet ^{[1
]}

Kabra, Sneha ^{[1
]}

Haldar, Subhasis ^{[2
]}

Gupta, R. S. ^{[1
]}

机构：

[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, New Delhi 110021, India

[2] Motilal Nehru Coll, Dept Phys, New Delhi 110021, India

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 02期

关键词：

surrounding gate MOSFET; graded channel profile; asymmetric gate stack; short channel effects; hot carrier effects;

D O I：

10.1016/j.sse.2007.09.006

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new structural concept, graded channel asymmetric gate stack (GCASYMGAS) SGT has been proposed and a two-dimensional analytical model is developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is shown that incorporation of ASYMGAS and graded channel designs leads to improved short channel immunity and hot carrier reliability. It is also demonstrated that for GCASYMGAS the average electric field in the channel is enhanced which leads to an increase in the electron velocity thereby improving the carrier transport efficiency. Furthermore, the device characteristics have been studied over a wide range of parameters and bias conditions and it is found that GCASYMGAS offers superior characteristics as compared to UD and GC devices. The results so obtained have been compared with simulated data obtained from the device simulator ATLAS 3D and are found to be in good agreement. (c) 2007 Published by Elsevier Ltd.

引用

页码：305 / 311

页数：7

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