Module generator of data recovery for serial link receiver

被引：0

作者：

Jou, SJ ^{[1
]}

Lin, CH ^{[1
]}

Chen, YH ^{[1
]}

Li, ZH ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Chungli 320, Taiwan

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A module generator for the all-digital data recovery of highspeed serial link using an oversampling method is proposed. The architecture of the proposed method is very regular and hence very suitable for standard cell implementation flow that makes it very suitable as a Soft Silicon Intellectual Property. This module generator can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. A design example generated by the module generator is implemented by using the TSMC 0.35 1P4M cell library. The maximum performance of the design (without extra pipelining stages) can reach 2.09 Gbps with power consumption of 112.2mW at 3.3V.

引用

页码：95 / 98

页数：4

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